GLOBALFOUNDRIES Achieves 14nm FinFET – Coming to New AMD Products

8 Comments

1. 

   Anonymous on November 6, 2015 at 4:57 pm

   What I want to ask AMD is
   What I want to ask AMD is will they be using their high density design libraries on their 14nm products like they used with Carrizo at 28nm. AMD got about 30% more plainer space savings on the already mature 28nm fab node for Carrizo without having to use a die shrink. So will AMD again be using high density design libraries for low power mobile parts, NOT desktop parts, for some Zen based variants. AMD can continue to use the standard low density high performance libraries for their desktop/server Zen variants. I’d like to see some mobile x86 APU, and custom ARM APU variants with more than 8 total ACE/compute units in addition to the 4 CPU cores. For mobile parts that using of high density design libraries appears to be a great idea to get more space out of any process node, and it’s not like any mobile variants need the use the low density high power design libraries that are use standard for CPU cores. Low power CPU/APU mobile chips are not going to be clocked that high anyways dew to thermal constraints.

   Someone needs to ask AMD, straight up, if their custom ARM cores are going to have SMT capabilities, as I have read discussions that maybe AMD’s Jim Keller run K12 and Zen design teams where using the same core execution engine design for both Zen and K12, and that it’s just that the Keller led design teams engineered their respective projects to run the x86, or ARMv8a ISAs. looking at Apple’s A7 and above(A8/A9 and X variants) custom Cyclone designs that are twice as wide order superscalar as the ARM reference designs(A53/A57/A72 cores) that compared to Apple’s custom cores with Cyclone’s twice the IPCs of ARM Holdings reference designs. How will AMD stack up against Cyclone if its custom ARM cores have SMT, while Apple does not use SMT in its Cyclone variants. SMT will allow for better effective IPC processing and better CPU core execution unit utilization with less execution pipeline under-utilization. So far none of the Custom, or refrence, ARM designs utilize SMT, and will AMD be the first. Imagination Technologies is offering a SMT enabled MIPS ISA based option for their latest MIPS/PowerVR based SOCs, so when will the ARM camp move in the direction of making SMT capable ARM CPU cores.

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     Hellowalkman on November 6, 2015 at 5:42 pm

     They might use it for mobile
     They might use it for mobile Zen ..

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       Anonymous on November 8, 2015 at 5:39 pm

       Mobile Zen for high end
       Mobile Zen for high end tablets, and on K12 for tablets, and maybe Phones in the future. Those high density design libraries normally used for GPU cores that run thousands of parallel FP/INT/Other units cannot be run at high frequency like CPU cores can with a CPU core’s relatively small amounts to FP/INT/SIMD units! So AMD with Carrizo utilizes the the high density design libraries for the Carrizo’s CPU cores and gets that 30% plainer die savings with the CPU core, so that 30% of extra space savings is available at 14nm also for parts that go into mobile devices that do not have the thermal headroom to run any companies’ CPU’s at high clock speeds anyways. Intel has to aggressively power gate its CPU cores on its mobile SKUs to fit in mobile parts in addition to down-clocking them, while AMD can design from the get go a part that is engineered to run at a lower clock rate while having more densely packed circuity via those high density design libraries.

       So imagine AMD’s K12 parts, an ARM custom ARMv8a ISA(RISC) running micro-architecture that uses the K12 custom ARM cores at 14nm. AMD will be able to implement the ARMv8a RISC instruction set with less transistors than the CISC(Complex Instruction Set Computing) x86 designs, and add to that using the high density design libraries on a custom ARMv8a ISA running core for 30% extra space savings on top of the spacing savings from going to 14nm! AMD will with ease be able to implement SMT into its custom ARMv8a ISA running cores, as well as retaining more die space to add more AMD ACE GPU units to its custom ARM APUs. Google would do well to approach AMD’s custom and semi-custom design division and commission a custom K12 ARM part for Google’s exclusive use, much like the console makers did with their custom console x86 parts. M$ and Sony have exclusive rights to their respective commissioned designs.

       AMD’s K12 will be very competitive, and if Jim Keller’s K12 design team baked SMT into the K12, then even Apple’s Cyclone is going to be at a disadvantage for the amount of IPCs that can be processed unless Apple goes SMT with its custom cores. If it’s true that Jim Keller’s design teams used the same core design tenets for both Zen and K12, and it’s only that each of Keller’s teams, Zen and K12, used the same execution engine but designed/made the execution engine to run the x86 ISA for the Zen and the ARMv8a ISA for K12, then K12 should have SMT abilities. The ARMV8a ISA takes less transistors to implement than the X86 ISA so those K12 custom ARM cores can have more cores per unit area than any x86 ISA core.

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     Anonymous on November 6, 2015 at 7:02 pm

     Given the power constraints,
     Given the power constraints, even on desktop, I have to wonder if they will use the high density libraries across the line. People don’t realize how power limited CPUs are. I see a lot of enthusiast complaining about the focus on mobile limiting the power of desktop CPUs, but this is probably not the case. At 14 nm the size of a CPU core, even a “large” core like Skylake, is down to maybe 10 to 12 square mm, including L1 and L2 caches. That is only a little over 3 mm on a side. This is absolutely tiny, and it is part of why we have so much other stuff integrated onto the die. If you try to run this tiny CPU at 4 GHz, that is a lot of heat out of a very small area. CPUs can still be thermally limited, even if they are not pushing against maximum power limits for the whole chip due to hot spots. Like AMD’s nano graphics card, it seems to be better to go wider at a lower clock and lower voltage. This doesn’t work as well with CPUs as it does with GPUs, but they can throw more hardware at the problem rather than pushing clock speeds to some extent.

     The previous excavator designs seemed to be geared more towards high clock; not as bad as the Pentium 4, but they were probably limited by hot spots and total power consumption due to the older process. Also, with how small CPU cores are, the CPU die is mostly other things. At this point, a CPU die is probably more memory hierarchy than anything else. The memory controllers, system agent, L3 caches, etc all take a lot more die area than a CPU core; it may be close to all of the CPU cores combined. These other components probably benefit a lot from the high density design libraries making it better to use the high density libraries over-all. If they are doing an HPC design on an interposer, they could much more easily us an optimal process for each component, but these will be very expensive parts.

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     Anonymous on November 6, 2015 at 7:30 pm

     I would expect that the K12
     I would expect that the K12 will have very similar specs to the Zen. They probably share a lot of design elements. A lot of units in the CPU are actually not instruction set specific. It could be the most powerful ARM based CPU, if it comes out in a reasonable amount of time. I am wondering if Apple plans on switching to ARM for all of their devices, and using AMDs ARM cores for their higher powered devices, at least until they can design their own ARM CPU of similar power.

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2. 

   Anonymous on November 6, 2015 at 7:31 pm

   The die on those wafers look
   The die on those wafers look quite large. I wonder if is a GPU wafer.

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3. 

   collie on November 7, 2015 at 6:40 am

   I may be alone in this
   I may be alone in this thinking, but it seems to me that we are approaching, ever so quickly (compared to techno evolution starting with non-passive fire) or ever so slowly, (compared to the last evolutionary transistor shrink within Moore’s law) to the 0.22nm that IS a carbon atom. So, while it’s all fine and good for some to be racing as small as possible as fast as possible, it seems that any good engineer should be slowing down, addressing the past knowledge and working on pushing the limits of modern understanding to new heights WITHIN the existing available technology.

   HOWEVER, I am tooooootaly BAKED right now, so who knows. I cant even tell you if that last bit was english.

   GOOD NIGHT CLEEVELAND!!!!! dont forget to tip your waitress!

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     donut on November 8, 2015 at 3:07 am

     That sounds like some good
     That sounds like some good stuff. How about passing it over here.

     Reply

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