If the rumours are true, the new 14nm Raven Ridge based AMD Ryzen 5 2500U will offer an impressive jump in performance compared to AMD's current generation of APUs. The Inquirer's source suggests the new APU will offer a 50% jump in single threaded performance and an impressive 90% advantage on multi-threaded performance. The multithreaded performance improvement may be the headline but seeing a huge increase in single threaded applications, AMD's recent Achilles Heel, shows some interesting improvements to Zen. This will also mark the arrival of their first APU with Vega onboard, so you can expect better graphics performance as well. The benchmark numbers and links are here.
"LEAKED BENCHMARKS for AMD's forthcoming Raven Ridge APUs suggest that upcoming devices, expected to be launched in time for Christmas, will outperform current Bristol Ridge APUs by up to 90 per cent on multicore applications."
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That is 8 excavator v2 cores
That is 8 excavator v2 cores (28 mm) against 4 core / 8 thread Ryzen (14 nm). Interesting that there is that large of multi-threaded difference also. It will be good to have some competitive AMD laptops.
All that Vega Graphics
All that Vega Graphics limited to 15 Watts on most Laptop OEM offerings will not be allowed to even breath. So Hopefully there will be some 35 Watt+ Raven Ridge APU SKUs offered for laptops. And the question still remaing, as far a Raven Ridge APUs are concerned, is what will AMD be using for HBC if the APUs do not come with any HBM2 to Act as HBC for Vega’s HBCC to make use of.
A Raven Ridge APU may as well be a Bristol Ridge as far as integrated graphics if the Raven Ridge APUs are all limited to 15 watt maximum form factor Laptop designs. Let’s hope that AMD, if these first Raven Ridge APUs do not have any HBM2 options, at least have some eDRAM or other larger cache provided or that Vega HBCC/HBC IP will have noting to work with.
I’m sure that there will be some Benifits to Vega’s nCU and DSBR/Primitive shader IP but Vega’s HBCC/HBC IP on the Raven Ridge APUs will have to be explaned fruther if there are no Mobule APUs that offer HBM2/HBC. So What will Raven Ridge use for HBC if there is no HBM2, and that’s what I want to know mostly, that and Raven Ridge laptop SKUs at 35+ watts for those that need better performance than can be had when restricted to only 15 watts.
I would expect Vega to
I would expect Vega to interface via IF. So we have a CCX with 4MB of L3 cache (attached to a dual channel DDR4 controler) and a Vega with IF and a 4MB L2 cache.
If AMD turn on the Title engine of Vega, 4MB will actually be decent.
But yes, the ultimate design would be a SoC 16GB of HBM2.
AMD could make 8GB and 16GB SoC, that should please most laptop customers.
I wonder if a single stack would be enough. 4GB and 8GB would be fine for the majority of laptops models.
Yes but there needs to be
Yes but there needs to be some Last/Level GPU cache below L2 to allow Vega’s HBCC/HBC IP to really shine and the HBC, if it’s not HBM2, needs to be eDRAM of at least 1/2GB-1GB to really make a difference. So a Raven Ridge APU, if it does not at least have one stack of HBM2, needs at least 1/2GB-1GB of something to act as HBC for the Vega HBCC to use as HBC/cache or that HBCC/HBC IP can not be utilized on Raven Ridge APUs.
That CPU L3(CPU only cache), if AMD’s raven Ridge Zen part of the Zen/Vega APU makes use of a single CCX unit, is not there for the Vega Graphics to make use of as that’s there for the Zen cores usage only. The Vega graphics, if it only uses the system’s DRAM below it’s L2 GPU cache is going to be starved for bandwidth even with the normally used 2, 128 bit memory channels to regular system DDR4 based DRAM.
It’s because one stack of HBM2 provdes for 8 independently operating 128 bit channels(1024 bits total). AND HBM2 has a Pseudo Channel mode for a double 64 bit(split from a single stack of HBM2’s 8, 128 bit channels) command rate compared to HBM1, if the HBM2 is not operated in Legacy mode. So HBM2(Even a single stack) has so much more effective bandwidth over system DDR4 DRAM.
So AMD better have provided some larger L2 GPU cache on it’s Vega APU graphics or some HBC/L3 cache that is eDRAM/SRAM based if there is no HBM2 stacks included.
Also note that HBM2 can be 3D stacked right on top of a processor instead of “2.5D” stacked next to the processor on an shared HBM2/Processor interposer package as is currently done with discrete Vega GPU SKUs. So that’s possible also for Raven Ridge also but who know yet.